Media Gateway Components

• Cisco MGX 8260 Hardware Installation Guide
  
  
• Cisco MGX 8260 Release Notes
  
  

• System Control Card (SCC)
  
  
• Distribution Matrix Card (DMC)
  
  
• Broadband Service Card (BSC)
  
  
• Narrowband Service Card (NSC)
  
  

DMCs, BSCs and NSCs are collectively known as service circuit cards. This subsection briefly describes the features and functions of each type of front card.

CPU

The central processing unit (CPU) maintains and executes the system functions of the MGX 8260. An R5000 type, 64-bit RISC processor serves as the CPU operating at an internal clock speed of 266 MHz and an external clock speed of 66.66 MHz.

An associated host bridge/memory controller handles SDRAM memory and provides device control via two independent 32-bit PCI interfaces. It also incorporates four DMA channels to transfer data between PCI ports on its dual PCI buses, its local SDRAM and input/output slave device.

The dual PCI interfaces operate at 33 MHz. PCI Bus A interfaces to an integrated SAR controller and an external BIM slot. PCI Bus B interfaces to two 10/100 Ethernet management ports and the PCI IDE controller.

Local data/program memory/packet buffer memory is stored on a 256 MB SDRAM module. SDRAM serves as the primary volatile memory system. It also "shadows" the flash memory so that performance is enhanced when running program memory.

Boot Flash Memory

Flash memory (2 MB) is used for boot strapping the CPU. The boot-up section is only 16 bits wide.

Flash Hard Disk

CSM

The CSM outputs 8 KHz and 192 KHz clock signals referenced by other devices. It also provide the following clocks to subsystems:

• 50/100 MHz clock to switch fabric section—ASX and ABM devices
  
  
• 66.6/75/83 MHz clock to CPU, L2 cache circuitry, SDRAM, system controller, EPLD etc.
  
  
• 33.3 MHz clock to PCI devices and PCI arbitration EPLD
  
  
• Cell Bus system clock
  
  
• Chip set clock distribution.
  
  
• Network clock
  
  

BIM

DMC Interface

An erasable programmable logic device (EPLD) serves as the controller and handles the signaling handshakes between the SCC and DMC.

Serial Ports

Cell Bus Controller

The ATMizer II scheduler block supports six levels of traffic priorities. The scheduler unit supports four independent calendar tables and performs traffic management functions on a large number of connections with arbitrary cell rates.

For additional processing flexibility, an enhanced direct memory access (DMA) controller performs the AAL5 SAR function in hardware. The ATMizer II+ device provides a 32-bit, 33 MHz PCI V-2.1 compliant bus interface for host access and a 32-bit 80 MHz local memory interface for data and control structures, and an 8-bit 50-MHz UTOPIA level-2 compliant port for PHY (OSI Layer 1) interface.

The Cell Bus interface consists of dual VLSI chips that implement ATM multiplexing and switching based on the Cell Bus architecture. The VLSI chip supports unicast and multicast transfers, cell address translation, cell routing and outlet cell queuing. Ingress and egress field programmable gate arrays (FPGAs) with custom application specific integrated circuits (ASICs) control ATM data cell transfer across the dual Cell Buses.

Switch Fabric

• ATM switch element (ASX)—functions as an 8 x 8 switching element connected to:
  
  
• ATM buffer manager (ABM) for the Cell Bus.
  
  
• ABM for BIM to FE or OC-3 ports
  
  
• ABM to individual BSCs (slots 11 to 16)
  
  
• Cell Bus ATM layer management (ALM)—connects the ABM with the switch fabric interface FPGA for receive and transmit operation across the bus
  
  
• Broadband ALM/ABM—manages FE and OC-3 input/output operations through SCC back card via the BIM
  
  

Environmental Monitoring

• Negative voltages: -48V for Feed A and Feed B
  
  
• Positive voltages: 5V, 3.3V, 2.5V, 1.5V
  
  
• Six temperature spots on the SCC
  
  
• Two temperature spots on the BIM
  
  
• One temperature spot on the CSM
  
  

Front and Back Cards

Status LEDs

LIU

M13 Multiplexer

Ingress data flows from the receive LIU to the M13 multiplexer. The incoming DS3 stream is demultiplexed into 28 separate DS1 streams. Separate data and clock signals are fed to the encoder FPGA block sitting downstream. For egress operations, M13 multiplexer receives clock and data signals for 28 separate DS1 streams from the decoder FPGA block and multiplexes them into a single DS3 stream. The DS3 stream is fed to the LIU transmit interface.

Encoder/Decoder Block

The encoder/decoder block uses a proprietary methodology to encode two separate clock and data streams into one stream before giving it to the midplane and vice versa decodes the encoded stream from the midplane into separate TDM clock and data signals. Six FPGAs implement six independent encoder/decoder blocks. Each FPGA block supports encoding and decoding for 28 T1 streams contained in a single DS3. Thus each block supports the encoding/decoding functions for individual DS3s.

Bit Switching Matrix

For ingress operation the 168 T1 streams demultiplexed from six DS3s enter as a single signal per T1 stream from the encoder block. In the same direction, the output of the switch matrix is connected to 192 streams routing to various midplane slots supporting NSCs on the MGX 8260 chassis.

In the egress direction, the 192 encoded streams coming from midplane are taken directly (after buffering), to the egress section of the switch matrix. All 192 inputs are copied to both the switching devices used in this block. The 168 output streams from this block are connected to the decoder block.

This distribution of inputs and outputs enables firmware to cross-connect any TDM stream from a DS3 to any TDM stream going to the midplane while avoiding contention between device outputs.

SCC Interface

An erasable programmable logic device (EPLD) serves as the controller and handles the signaling handshakes between the SCC and DMC.

Clock Synchronization

The DMC generates a 44.736 MHz clock to be used as the transmit clock for the DS3 interfaces. The clock generator is a phase locked loop (PLL) synthesizer which accepts an 8KHz clock signal as an input reference.

The DMC is also capable of supplying two separate 8-KHz references to the midplane as primary and secondary reference clocks. The source for each of these references is selectable individually from any of the incoming six DS3 streams. Each of these reference clock signals has an individual tri-state control.

Digital Temperature Sensor and Thermal Watchdog

Loopback Support

• Local line loopback is configured at the LIU interface. The transmit line signals are connected to the receive line signals after B3ZS encoding. This is a local loopback on the DS3 level.
  
  
• Remote line loopback is configured at the LIU interface. The transmit line signals are connected to the receive line signals before B3ZS encoding. This is a local loopback on the DS3 level.
  
  
• DS3 metallic loopback causes all the DS3 lines to loopback simultaneously; loopback control of individual DS3s is not currently offered.
  
  

Front and Back Card

Status LEDs

CPU

The central processing unit (CPU) maintains and executes the broadband interface functions of the BSC. An R5000 type, 64-bit RISC processor serves as the CPU operating at an internal clock speed of
266 MHz and an external clock speed of 66.66 MHz.

An associated host bridge/memory controller handles SDRAM memory and provides device control via two independent 32-bit PCI interfaces. It also incorporates four DMA channels to transfer data between PCI ports on its dual PCI buses, its local SDRAM, and an input/output slave device.

The dual PCI interfaces operate at 33 MHz and interface to integrated SAR and HDLC controllers, as well as the switch port fabric.

Local data/program memory/packet buffer memory is stored on a 256 MB SDRAM module. SDRAM serves as the primary volatile memory system. It also "shadows" the Flash memory so that system performance is enhanced.

Boot Flash Memory

Flash memory (2MB) is used for boot strapping the CPU. The boot-up section is only 16-bits wide.

AAL5—SAR

The hardwired SAR functionality is optimized for AAL5 traffic. Connections with different quality of service (QoS) parameter values are efficiently scheduled and serviced via an integrated hardware scheduler that supports up to four priority classes. The scheduler uses calendar tables to create arbitrary traffic schemes to a limit of 64K virtual connections.

The device's memory controller provides a glueless interface with synchronous DRAMs that are used for local memory, while also serving as a control interface for external physical layer devices.

The primary interface for the device is a 33 MHz, 32-bit wide PCI bus. As the bus master, the ATMizer is able to autonomously access control and data structures in system memory. As a bus slave, the device provides transparent access to local memory and to the internal cell buffer for external PCI bus masters. The PCI interface also implements four separate first in/first out (FIFO) buffers to maximize the performance of simultaneous read/write operations as bus master or slave.

The ATMizer uses 16 MB of SDRAM as its program and data memory. For maintaining configuration and control tables, 512 KB of SSRAM is provided.

The ATMizer's PCI bus runs at 33 MHz whereas the core CPU runs at 40 MHz via an independent oscillator.

Switch Port Fabric

The BSC's switch port fabric does the following:

• Operates in a full duplex mode with a maximum ATM cell traffic rate of 622 Mbps in each direction.
  
  
• Ingress side processes cells arriving from the ATM switch fabric located on the SCC.
  
  
• Egress side processes cells being sent to the ATM switch fabric located on the SCC.
  
  
• Input and output ports connect the switch port fabric's ABM/ALM with the midplane for receive and an transmit operations. The ABM interfaces with the ASX located on the SCC. The ALM transfers data to/from the SCC BIM.
  
  

AAL1 SAR

HDLC Controllers

M13 Multiplexer

Ingress data flows from the receive LIU to the M13 multiplexer. Demultiplexing is done on this incoming stream. Separate data and clock signals are then fed to the octal framer block sitting downstream, as 28 separate DS1 signals. In the egress direction, the M13 multiplexer receives clock and data signals for 28 separate DS1 streams from the octal framer block, multiplexes these incoming streams as a single DS3 signal and feeds it to the transmit line interface.

Octal Framers

The octal framer block performs the following tasks:

The line transceiver contains both the receiver and transmitter to support the DS3 (44.736 Mbps) data rate.

For egress operation, the transceiver accepts digital clock and data from a framer. It encodes the data (B3ZS), and converts it into the appropriate pulse shapes for transmission over coaxial cable. For ingress operation, the transceiver accepts a bipolar signal from the DS3 transmit line, performs B3ZS decoding, converts the line signal into a dual rail binary data stream, recovers the clock, decodes the data, and coverts it back into a dual rail digital signal.

Front and Back Card

Status LEDs

When direct physical T1 or E1 network connections are required, the NSC is paired with a back card that provides the T1/E1 connectors. A designated NSC supports optional 1:N redundancy when equipped with a special redundant back card.

NSCs can be placed in slots 1 to 8, and slots 11 to 16 (maximum 14 cards per chassis).

CPU

The central processing unit (CPU) maintains and executes the interface functions of the NSC. An RM7000 type, 64-bit RISC processor serves as the CPU operating at an internal clock speed of 263 MHz and an external clock speed of 66.66 MHz.

An associated host bridge/memory controller handles SDRAM memory and provides device control via two independent 32-bit PCI interfaces. It also incorporates four DMA channels to transfer data between PCI ports on its dual PCI buses, its local SDRAM and an input/output slave device.

The dual PCI interfaces operate at 33MHz and interface to integrated SAR controllers, as well as MSMs.

Local data/program memory/packet buffer memory is stored on a 256MB SDRAM module. SDRAM serves as the primary volatile memory system. It also "shadows" the flash memory so that performance is enhanced when running program memory.

Boot Flash Memory

Flash memory (2 MB) is used for boot strapping the CPU. The boot-up section is only 16 bits wide.

Cell Bus Controller

The Cell Bus interface consists of dual VLSI chips that implement ATM multiplexing and switching based on the Cell Bus architecture. The VLSI chip supports unicast and multicast transfers, cell address translation, cell routing and outlet cell queuing. Ingress and egress field programmable gate arrays (FPGAs) with custom application specific integrated circuits (ASICs) to control ATM data cell transfer across the dual Cell Buses.

CES-AAL1

AAL5—SAR

The hardwired SAR functionality is optimized for AAL5 traffic. Connections with different quality of service (QoS) parameter values are efficiently scheduled and serviced via an integrated hardware scheduler that supports up to four priority classes. The scheduler uses calendar tables to create arbitrary traffic schemes to a limit of 64K virtual connections.

The device's memory controller provides a glueless interface with synchronous DRAMs that are used for local memory, while also serving as a control interface for external physical layer devices.

The primary interface for the device is a 33 MHz, 32-bit wide PCI bus. As the bus master, the ATMizer is able to autonomously access control and data structures in system memory. As a bus slave, the device provides transparent access to local memory and to the internal cell buffer for external PCI bus masters. The PCI interface also implements four separate first in/first out (FIFO) buffers to maximize the performance of simultaneous read/write operations as bus master or slave.

The ATMizer uses 16 MB of SDRAM as its program and data memory. For maintaining configuration and control tables, 512 KB of SSRAM is provided.

The ATMizer's PCI bus runs at 33 MHz whereas the core CPU runs at 40 MHz via an independent oscillator.

Clock Synchronization

The clock circuitry also sources clock signals to the following subsystems:

• 66 MHz clock to CPU, L2 cache circuitry, SDRAM, system controller, EPLD etc.
  
  
• 33.3 MHz clock to PCI devices and PCI arbitration EPLD
  
  
• 40MHz clock to SAR (AAL5), MSM, and the Cell Bus
  
  
• 50MHz clock to MSM for the DSPs, Encoder-Decoder FPGA, Rate Changer FPGAs
  
  
• 38.88MHz clock to the CES (AAL1) devices
  
  
• 20MHz clock to CES-ALL1 bus
  
  

MSM Slots

• 32-bit PCI bus which connects to PCI Bus A
  
  
• 16-bit processor interface
  
  
• FPGA programming interface
  
  
• EEPROM interface
  
  
• Four PCM highways (totaling 32 Mbps) per slot
  
  
• Eight framer digital interfaces (used for PCM bypass)
  
  

LIU

• Transmit Data (TPCM)
  
  
• Receive Data (RPCM)
  
  
• Transmit Signalling (TSIG)
  
  
• Receive Signalling (RSIG)
  
  

The 8-Mbps PCM streams are connected to two MSMs through a digital switch device.

TDM Switch

The digital switches handle the PCM data between the framers, MSM and the Rate Changer FPGA. The connectivity between the switches ensures cross connectivity between all the CES-AAL1 devices and MSMs.

Rate Changer/FPGA

The FPGA changes the bit rate in the ingress direction from the digital switch device at 8 Mbps to the CES-ALL1 TDM interface at 2Mbps. In the egress direction, the FPGA takes in 16 TDM streams (synchronous to each other), from the CES-AAL1. Every four of these are combined to make one MVIP stream at 8Mbps which is connected to a digital switching device. Thus a total of four MVIP streams are formed from 16 input streams.

DMC Interface

The encoder/decoder FPGA uses Manchester encoding/decoding to encode T1 clock and data signals into one signal and decode the encoded signal into separate T1 clock and data signals.

Front and Back Cards

Status LEDs

• SCC with FE connectors
  
  
• SCC with OC-3 connectors (single mode fiber)
  
  
• DS3 with SMB connectors
  
  
• T1/E1 with 50-pin connectors
  
  
• E1 with RJ48 connectors
  
  
• T1/E1 redundant
  
  

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Note   Refer to the Cisco MGX 8260 Hardware Installation Guide for a comprehensive list of individual connector pinouts.

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• Operating system
  
  
• Switch application
  
  
• Optional applications
  
  

This subsection briefly describes these software components.

• High-performance real-time kernel—includes multitasking with preemptive priority scheduling, intertask synchronization and communications facilities, interrupt handling support, watchdog timers, and memory management.
  
  
• I/O system—supports UNIX standard buffered I/O and includes the following drivers.
  
  
• Network driver—for network devices (Ethernet, shared memory)
  
  
• Pipe driver—for intertask communication
  
  
• RAM "disk" driver—for memory-resident files
  
  
• Local file systems—tailored to real-time applications.