|
This appendix describes Autotest under debug and error code and contains the following sections:
When you power on the FastPAD, it will start the Autotest. The startup tests can be checked for problems by using the front panel or under Dbug. (See Figure D-1.)
When the power is switched on, the execution of the autotests will start after some seconds. In case of an error during one of the tests, the number of the test will be shown by the LEDs for four seconds. When the error is a major one, the autotests will be restarted: when the error is minor, the tests will be continued.
After a third major error, the tests will be stopped and the erroneous test number will be displayed by the LEDs.
The error code is byte-coded by quartet.
See Figure D-2 for the setup of the LEDs on the front panel during the test.
When an OPALE cable is used on the front panel (DIN connector), a terminal can use the system monitor via DB-25, to view autotests in clear language.
Figure D-3, Figure D-4, and Figure D-5 list the meaning of the LEDs during startup tests. Table D-1 lists the meaning of front panel LED activity during mp6 startup.
Test Number | Meaning |
---|---|
| "CONFIG" LED FLASHED |
| 68302 TESTS (SP BOARD) |
(10) (11) (12) (13) | RAM test (zone A) writing 00, reading. RAM test (zone A) writing/reading bytes with travelling bit. RAM test (zone B) writing 00, reading. RAM test (zone B) writing/reading bytes with travelling bit. |
(11) | RAM test (zone A) writing/reading bytes with travelling bit. |
(12) | RAM test (zone B) writing 00, reading. |
(13) | RAM test (zone B) writing/reading bytes with travelling bit. |
(20) (21) | BOOT PROM Check sum of the Boot Flash PROM. Identification of the Boot Flash manufacturer code. |
(22) (23) (24) | APPLI PROM Check of the application Flash PROM According result of check/identification update checklist Check sum of application PROM. |
(30) (31) (32) (33) (34) (35) | RAM/SMART WATCH Determine type of component (EEPROM or RAM with clock) Identification zone if validation word absent, major error. If validation word present: test check sum. Check the size of the component: conformity test check/identification. User's rights zone: test check sum when programmed. Software configuration zone: test check sum when programmed. |
(40)
(41) | DYNAMIC RAM Check RDDC. Conformity check/identification result. Update check table. Test of RDDC not tested before. Write 00 and traveling "1" bit. |
(50) | DUART Test Channel B: internal loop. |
(60) | CLOCK Determine clock frequency of 68302 micro-processor. |
(70) (71) (72) (73) (74) (75) (76) | IMP 68302 Check the 68302 slave. Test SSC1 of the 68302 master. Test SSC2 of the 68302 master. Test SSC3 of the 68302 master. Test SSC1 of the 68302 checked slave. Test SSC2 of the 68302 checked slave. Test SSC3 of the 68302 checked slave. |
(80) | ISDN INTERFACE Check presence of interface on line 0. |
Autotest monitored with Dbug for an mp using an ISDN interface:
RESET GENERAL !!!!
*** ENVIRONMENT : A ***
RAM MIN
PROM BOOT
PROM APPLI
RAM/SMART WATCH
DYNAMIC RAM
DUART
MEMORY CARD
CLOCK
Imp 68302
INTERFACE RNIS
*** ENVIRONMENT : B ***
PROM BOOT
PROM APPLI
RAM/SMART WATCH
DYNAMIC RAM
DUART
MEMORY CARD
Imp 68302
>>> Tests OK <<<
Autotest monitored with Dbug for an mp12 or mprxx. In that case a transputer zone is checked:
RESET GENERAL !!!!
*** ENVIRONMENT : A ***
RAM MIN
PROM BOOT
PROM APPLI
RAM/SMART WATCH
DYNAMIC RAM
DUART
MEMORY CARD
CLOCK
Imp 68302
*** ENVIRONMENT : B ***
PROM BOOT
PROM APPLI
RAM/SMART WATCH
DYNAMIC RAM
DUART
MEMORY CARD
Imp 68302
*** ENVIRONMENT : TRANSPUTER ***
>>> Tests OK <<<
Autotest with a checksum error.
The system will try to start three times and stays in halt mode. The front panel indicates the error code.
RESET GENERAL !!!!
*** ENVIRONMENT : A ***
RAM MIN
PROM BOOT
PROM APPLI
RAM/SMART WATCH
*** ENVIRONMENT : A ***
PROM BOOT
PROM APPLI
RAM/SMART WATCH
*** ENVIRONMENT : A ***
PROM BOOT
PROM APPLI
RAM/SMART WATCH
>>> Tests not OK : error 32 <<<
Posted: Thu Jan 25 14:09:56 PST 2001
All contents are Copyright © 1992--2001 Cisco Systems, Inc. All rights reserved.
Important Notices and Privacy Statement.