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nPartition Administrator's Guide > Chapter 3 Planning nPartitions

Configuration Requirements for nPartitions

 

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The hardware requirements determine which cells are eligible to be assigned to an nPartition.

For configuration requirements and restrictions for Superdome hybrid servers, refer to “HP Superdome Hybrid Servers: Intel Itanium 2 and PA-RISC nPartition Mixing”. HP Superdome servers based on the HP sx1000 chipset can support hybrid configurations with both PA-RISC nPartitions and Intel Itanium 2 nPartitions in the same server complex.

Every nPartition you configure must meet the following hardware requirements:

  • On HP 9000 systems, all cells in an nPartition must have the same processor revision level and clock speed. That is, the IODC_HVERSION must be identical for all PA-RISC processors.

    You can view processor details, including the CPU type (revision level) and speed, by using the parstatus -V -c# command or by using Partition Manager (select the Cell->Show Cell Details action, CPUs/Memory tab).

  • On HP Integrity servers, all cells in an nPartition must have the same compatibility value.

    The cell compatibility value is reported by the parstatus -V -c# command as "CPU Compatibility" for the cell.

    Partition Manager Version 2.0 reports the value as "Cell Compatibility" in the General Cell Properties view for the cell, which you can display by clicking the cell location when viewing other details about the server complex.

  • On HP Integrity servers, all cells assigned to an nPartition must have either mx2 dual-processor modules or single Itanium 2 processors.

    Both HP mx2 dual-processor modules and single Itanium 2 processors can exist in the same complex, but they cannot be mixed in the same nPartition.

  • The same firmware revision must be present on all cells within an nPartition.

  • At least one cell in every nPartition must be connected to an I/O chassis that has core I/O.

    Only one core I/O is active per nPartition. If an nPartition has multiple cells that are connected to I/O chassis with core I/O, only the core I/O connected to the active core cell is active.

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